Variable Word Width Computation for Low Power

Today’s mobile processors must often times tackle a multitude of computing applications, many of which do not require the full 32-bit data word for their computations. In light of this, it is possible to restrict the computations for these applications to a reduced width data word to minimize power consumption. A modification to a standard RISC architecture is presented to reduce the overall power consumption of these reduced-width applications. The processor is modified to allow computations to be performed on either 32-bit or 16-bit wide data. Instructions remain 32 bits, and 32bit memory calculations can be interspersed with 16-bit data operations. An analysis is presented of the approximate power savings of a processor employing these modifications over the same processor without these modifications.